1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a gate electrode formed by using a hard mask and a method of manufacturing the semiconductor device.
2. Description of the Background Art
In a semiconductor device having a gate electrode, conventionally, precision in a dimension of the gate electrode greatly influences a variation in characteristics of individual semiconductor elements and the influence is further increased with an enhancement in integration of the semiconductor device. For example, substrate reflection is prevented by using an inorganic or organic reflecting preventive film (such as an SiN film, an SiON film or the like which is formed by plasma CVD) during exposure of a resist and a thickness of the resist is reduced in order to enhance a resolution of a gate pattern. In particular, the reduction in the thickness of the resist tends to further progress with an increase in the integration of the semiconductor device in recent years.
In general, there are mainly two different methods of forming a gate electrode. As one of the methods, a resist is formed on a gate electrode material and the gate electrode material is subjected to etching by using the resist itself as a mask. As the other method, a film having a very high etching resistance to the gate electrode material (which will be hereinafter referred to as a “hard mask”) is deposited on the gate electrode material, and a resist is first formed on the hard mask, the hard mask is subjected to etching by using the resist as a mask and the resist is removed, and subsequently, the gate electrode material is subjected to the etching by using the patterned hard mask as a mask.
FIGS. 24A and 24B are views for explaining a process for forming a gate electrode by the method of etching a gate electrode material using a resist as a mask. In FIGS. 24A and 24B, the reference numeral 101 denotes a semiconductor substrate, the reference numeral 102 denotes a gate insulating film, the reference numeral 103 denotes a gate electrode material and the reference numeral 104 denotes a resist. As shown in FIG. 24A, first of all, the gate insulating film 102 and the gate electrode material 103 are deposited on the semiconductor substrate 101 and the resist 104 is formed on the gate electrode material 103. As shown in FIG. 24B, the gate electrode material 103 and the gate insulating film 102 are subjected to etching by using the resist 104 as a mask so that a gate electrode 110 is formed. At this time, an etching selectivity for the gate electrode material 103 of the resist 104 is not very great. Therefore, it is apparent that the resist 104 is also etched greatly when the gate electrode material 103 is etched, resulting in a great reduction in the film. For this reason, it is necessary to previously form the resist 104 sufficiently thickly.
On the other hand, FIGS. 25A to 25C are views for explaining a process for forming a gate electrode by the method of etching a gate electrode material using a hard mask as a mask. In FIGS. 25A to 25C, the same components as those in FIGS. 24A and 24B have the same reference numerals. Moreover, the reference numeral 105 denotes a hard mask. As shown in FIG. 25A, first of all, a gate insulating film 102, a gate electrode material 103 and the hard mask 105 are deposited on a semiconductor substrate 101 and a resist 104 is formed on the hard mask 105. Examples of a film to be used for the hard mask 105 include an SiO film, an SiN film and the like which are formed by CVD, for example. As shown in FIG. 25B, next, the hard mask material 105 is subjected to the etching by using the resist 104 as a mask and the resist 104 is then removed. As shown in FIG. 25C, the gate electrode material 103 and the gate insulating film 102 are subjected to the etching by using the hard mask 105 as a mask so that a gate electrode 110 is formed. At this time, since the hard mask 105 has a very high etching selectivity for the gate electrode material 103, a reduction in a film of the hard mask 105 is lessened during the etching. For this reason, it is not necessary to greatly increase the thickness of the hard mask 105 during formation. In other words, when the gate electrode material 103 is to be etched, a thickness of a mask (that is, the hard mask 105) can be reduced so that precision in a dimension of the gate electrode 110 to be formed can be enhanced.
Moreover, the hard mask 105 has such an advantage that the gate electrode 110 can be prevented from being unnecessarily etched by the presence of the hard mask 105 on an upper surface of the gate electrode 110 in the case in which the gate electrode 110 is to be used as a mask in a self-alignment process.
In general, the resist 104 can easily be removed, while the hard mask 105 is removed with difficulty and is to be removed by etching. In the case in which the hard mask 105 is to be removed, therefore, a process for manufacturing a semiconductor device becomes complicated. Moreover, portions other than the hard mask 105 (the gate electrode 110, a wafer surface, an insulating film and the like) are influenced by the etching. Consequently, there is a possibility that a characteristic of the semiconductor device might be changed.
For example, in the case in which the hard mask 105 remains on the upper surface of the gate electrode 110 when the gate electrode 110 is to be salicided (SAlicide: Self Aligned Silicide) or a contact is to be formed on the gate electrode 110, it is necessary to remove the hard mask 105.
The gate electrode 110 is salicided by depositing a saliciding reactive material 111 on the gate electrode 110 to carry out a heat treatment. In this case, if the hard mask 105 is not present on the gate electrode 110 as shown in FIG. 26A, a salicide region 112 is formed on the upper surface of the gate electrode 110 which is provided in contact with the saliciding reactive material 111. However, if the hard mask 105 is present on the gate electrode 110 as shown in FIG. 26B, the upper surface of the gate electrode 110 cannot directly come in contact with the saliciding reactive material. Therefore, the salicide region cannot be formed in that state.
Moreover, it is supposed that an interlayer insulating film 113 is formed on the gate electrode 110 and a contact reaching the gate electrode 110 is formed on the interlayer insulating film 113 as shown in FIGS. 27A and 27B. In this case, if a hard mask is not present on the gate electrode 110, it is preferable that only the interlayer insulating film 113 provided on the gate electrode 110 should be etched to form a contact hole as shown in FIG. 27A. However, if the hard mask 105 is present on the gate electrode 110, it is necessary to etch the interlayer insulating film 113 provided on the gate electrode 110, and furthermore, the hard mask 105 as shown in FIG. 27B. Consequently, a step of forming the contact hole becomes complicated.